====== AMD Ryzen AI Pro 400 Series ======

The **AMD Ryzen AI PRO 400 Series** processors are enterprise-grade chips that combine Zen 5 CPU cores, RDNA 3.5 integrated graphics, and a dedicated XDNA 2 Neural Processing Unit delivering up to 50 TOPS of AI compute. Announced at CES 2025 and expanded at MWC 2026, they represent the first desktop processors to qualify for Microsoft's Copilot+ PC certification. ((Source: [[https://www.amd.com/en/blogs/2026/amd-ryzen-ai-pro-400-series-cpus-deliver-advanced-ai-for-desktops.html|AMD — Ryzen AI PRO 400 Series for Desktops]]))

===== Architecture =====

The 400 Series combines three processing engines on a single piece of silicon:

  * **Zen 5 CPU Cores** — Hybrid design mixing Zen 5 performance cores and Zen 5c efficiency cores for balanced multithreading and power efficiency
  * **RDNA 3.5 Graphics** — Integrated GPU for AI-accelerated video editing, 3D rendering, and display output
  * **XDNA 2 NPU** — Second-generation neural processing unit delivering up to 50 TOPS of dedicated AI compute

The processors are fabricated on a **4nm process** (Gorgon Point architecture). ((Source: [[https://awesomeagents.ai/news/amd-ryzen-ai-400-desktop-npu/|Awesome Agents — AMD Ryzen AI 400]]))

===== Desktop SKUs =====

^ Model ^ Cores ^ Configuration ^ Boost Clock ^ GPU ^ L3 Cache ^ TDP ^
| Ryzen AI 7 450G/GE | 8C/16T | 4 Zen 5 + 4 Zen 5c | 5.1 GHz | Radeon 860M (8 CU) | 16 MB | 65W/35W |
| Ryzen AI 5 440G/GE | 6C/12T | 3 Zen 5 + 3 Zen 5c | 4.8 GHz | Radeon 840M (4 CU) | 16 MB | 65W/35W |
| Ryzen AI 5 435G/GE | 6C/12T | 2 Zen 5 + 4 Zen 5c | 4.5 GHz | Radeon 840M (4 CU) | 8 MB | 65W/35W |

All six desktop chips share the same 50 TOPS XDNA 2 NPU. The "G" variants run at 65W TDP while "GE" variants run at 35W for mini PCs and embedded systems. All use the **AM5 socket** with **DDR5-5600** memory. ((Source: [[https://awesomeagents.ai/news/amd-ryzen-ai-400-desktop-npu/|Awesome Agents — AMD Ryzen AI 400]]))

PRO variants (Ryzen AI PRO 450G, 440G, 435G) add enterprise security and fleet management features.

===== XDNA 2 NPU =====

The XDNA 2 architecture is AMD's second-generation neural processing unit:

  * Delivers up to 50 TOPS on desktop (up to 60 TOPS on select mobile PRO variants)
  * Exceeds the 40 TOPS minimum required for Microsoft Copilot+ PC certification
  * Surpasses Intel's desktop Arrow Lake NPU (approximately 13 TOPS) by nearly 4x
  * Supports on-device AI workloads including local LLM inference, image generation, and real-time translation ((Source: [[https://www.windowscentral.com/hardware/cpus/amd-ryzen-ai-pro-400-series-announcement-mwc-barcelona|Windows Central — AMD Ryzen AI PRO 400]]))

===== Enterprise Features (PRO) =====

The AMD PRO platform adds capabilities for IT fleet management:

  * **AMD PRO Security** — Hardware-rooted security with AMD Memory Guard and Secure Processor
  * **AMD PRO Manageability** — Remote management capabilities for enterprise fleet administration
  * **Standardization** — Unified NPU performance across desktop and laptop form factors, avoiding software compatibility fragmentation during fleet refresh cycles ((Source: [[https://www.amd.com/en/blogs/2026/amd-ryzen-ai-pro-400-series-cpus-deliver-advanced-ai-for-desktops.html|AMD — Ryzen AI PRO 400 Series for Desktops]]))

===== Competitive Position =====

^ Feature ^ AMD Ryzen AI PRO 400 ^ Intel Arrow Lake (Desktop) ^ Qualcomm Snapdragon X ^
| NPU Performance | Up to 50 TOPS | ~13 TOPS | 45 TOPS |
| Copilot+ Qualified | Yes | No (below 40 TOPS threshold) | Yes |
| CPU Architecture | Zen 5 (hybrid) | P-core/E-core | Arm (Oryon) |
| Socket | AM5 (desktop) | LGA 1851 | BGA (laptop only) |
| Form Factors | Desktop + Laptop | Desktop + Laptop | Laptop only |

AMD is the first to bring Copilot+ qualified NPU performance to the desktop form factor, with OEM partners HP, Lenovo, and Dell announcing systems. ((Source: [[https://awesomeagents.ai/news/amd-ryzen-ai-400-desktop-npu/|Awesome Agents — AMD Ryzen AI 400]]))

===== See Also =====

  * [[neural_processing_unit|Neural Processing Unit (NPU)]]
  * [[ai_native_chiplet|AI-Native Chiplet Architecture]]

===== References =====