====== HBM4E High-Bandwidth Memory ======

**HBM4E (High Bandwidth Memory 4E)** is an enhanced variant of HBM4 DRAM designed for AI accelerators and high-performance computing. Featuring a 2048-bit interface and data rates up to 16 Gb/s, HBM4E delivers up to 4.096 TB/s bandwidth per stack — a generational leap enabling the massive memory throughput demanded by frontier AI models. ((Source: [[https://semiengineering.com/hbm4e-raises-the-bar-for-ai-memory-bandwidth/|SemiEngineering — HBM4E Raises the Bar]]))

===== Technical Specifications =====

^ Generation ^ Data Rate (Gb/s) ^ Interface Width (bits) ^ Bandwidth/Stack (TB/s) ^ Max Stack Height ^ Max Capacity (GB) ^
| HBM3E | 9.6-9.8 | 1024 | 1.2 | 16-high | 48-64 |
| HBM4 | 8-11+ | 2048 (32 channels) | 1.64-2.8+ | 12-16-high | 36-64 |
| HBM4E | 10-16 | 2048 | 2.5-4.096 | 16-high | 64 |

Key advances in HBM4 and HBM4E include doubling the channel count from 16 to 32, lower operating voltages (0.7V VDDQ), Directed Refresh Management (DRFM) for reliability at AI operating temperatures, and customizable base dies for tight integration with AI GPUs. ((Source: [[https://www.rambus.com/blogs/hbm3-everything-you-need-to-know/|Rambus — HBM Everything You Need to Know]]))

===== Developers =====

Three major memory manufacturers are competing in the HBM4/HBM4E space:

  * **SK Hynix** — Developed the world-first 12-layer HBM4 (September 2025) with 2048 I/O channels and over 40% power efficiency improvement ((Source: [[https://news.skhynix.com/sk-hynix-showcases-advanced-ai-memory-at-sc25/|SK Hynix — SC25 AI Memory]]))
  * **Micron** — Leading HBM4E development with 1-beta (5th gen 10nm-class) DRAM on a 2048-bit base die; high-volume HBM4 production (36GB 12-high stacks) delivering over 2.0 TB/s per stack and 20%+ power efficiency gains over HBM3E ((Source: [[https://www.micron.com/products/memory/hbm|Micron — HBM]]))
  * **Samsung** — Developing HBM4 at 13 Gb/s on 4nm logic base die for next-generation AI GPUs ((Source: [[https://www.tomshardware.com/pc-components/gpus/microns-hbm4e-heralds-a-new-era-of-customized-memory-for-ai-gpus-and-beyond|Tom's Hardware — Micron HBM4E]]))

===== Timeline =====

HBM4 entered production in 2025, with SK Hynix and Micron shipping 12-layer stacks. HBM4E targets 2027 production, with controller IP (e.g., from Rambus) already supporting 16 Gb/s data rates. ((Source: [[https://introl.com/blog/hbm-evolution-hbm3-hbm3e-hbm4-memory-ai-gpu-2025|Introl — HBM Evolution]]))

===== AI Accelerator Integration =====

HBM4E is designed for next-generation AI GPUs, training systems, and HPC platforms. An 8-stack configuration can deliver 32.768 TB/s aggregate bandwidth — sufficient for frontier models with trillions of parameters. Target platforms include:

  * NVIDIA Vera Rubin GPUs (288 GB HBM4 at 22 TB/s per GPU)
  * AMD Instinct accelerators
  * Custom AI silicon from hyperscalers

The customizable base die approach pioneered by Micron's HBM4E allows memory manufacturers to tailor the logic die for specific AI accelerator requirements, optimizing power delivery and signaling for each platform. ((Source: [[https://www.tomshardware.com/pc-components/gpus/microns-hbm4e-heralds-a-new-era-of-customized-memory-for-ai-gpus-and-beyond|Tom's Hardware — Micron HBM4E]]))

===== See Also =====

  * [[nvidia_vera_rubin|Nvidia Vera Rubin]]
  * [[ai_native_chiplet|AI-Native Chiplet Architecture]]
  * [[sram_centric_chips|SRAM-Centric Chips]]

===== References =====